Modern semiconductor industry has provided a revolution in our lives and has been the foundation for developing computer industry and electronic devices we now cannot live without. The economic significance of the semiconductor industry in our society is of utmost importance.
Behind this scientific, technical and economic evolution is the material science of semiconductor materials. Transistors, lasers and solar cell assemblies converting light into electricity etc. relies on cheap and reliable semiconductor materials. However, there are still needs for improvements in the material properties, for example increasing speed and limiting power consumption in transistors, providing more efficient lasers and lately improving the electric power output from semiconductor solar cells. When it comes to solar cell assemblies it is also of utmost importance to provide semiconductor materials providing highest possible efficiency at the lowest possible cost of materials. It is also important to be able to produce huge quantities of semiconductors with a high yield factor. All these desired properties of semiconductors may be fulfilled completely or partially by manufacturing semiconductor materials with the correct physical properties, as known to a person skilled in the art, as basis materials for these semiconductor devices and manufacturing thereof.
In the field of semiconductor material science it is well known that gallium arsenide (GaAs) has many desirable properties as a foundation for semiconductors. The mobility and other physical properties of this material can increase the speed of semiconductor devices made from this material significantly compared with the more traditional semiconductor materials like silicon (Si). As known to a person skilled in the art, Si is however much cheaper than GaAs. Therefore, manufacturing of a semiconductor material comprising GaAs on top of a Si wafer is a desirable material combination. Manufacturing of transistors would then provide a high frequency device combined with known Si integrated circuit technology, solar cells would have high efficiency at a low price and lasers could be manufactured with larger scale production with cheaper substrates. Further, integration of optical devices on a same chip comprising integrated electronic circuits will be facilitated.
These preferable properties have been known for a long time in the prior art. However, growing high quality mono-crystalline GaAs on mono-crystalline silicon is not trivial due to the large lattice mismatch of the two materials. When combining these materials, for example in an epitaxial growth process, as known to a person skilled in the art, the lattice mismatch leads to stacking of faults, denoted threading dislocations, that ruins the physical properties necessary for making semiconductor devices that fulfils the desired requirements. The threading dislocations appear for example in a GaAs layer that is being grown on top of a Si wafer. The threading dislocations will have a certain orientation relative to the epitaxial growth direction and the dominant direction is usually close to being parallel or is parallel with the growing direction. The length of the threading dislocations may be shorter than the end thickness of the grown layer, but thickness of layers in semiconductor devices contributes significantly to what kind of physical properties the material will provide as a basis for a semiconductor device, as known to a person skilled in the art. Even though the length of the threading dislocations may be limited, the physical property of the interface between the different materials still needs to be controlled.
In prior art there are known some examples of experimental processes trying to achieve a combination of for example GaAs as a III-V material on non III-V materials that has used relative thick buffer layers and/or strained-layer super lattices to reduce defect densities. For example, a transition, super-lattice and/or buffer layer with a thickness of 1000 Å or more is reported used in experimental methods. This is essential, since such a dimension of a layer with no other function than being a buffer will create extra material costs and production time in addition to being detrimental to device performance. For example: In a solar cell application, this layer will contribute with additional impedance and the layer may absorb light without generating electricity.
M. Yamaguchi, M. Tachikawa, Y. Itoh, M. Sugo, S. Kondo: “Thermal annealing effects of defect reduction in GaAs on Si substrates.”, Journal of Applied Physics, Vol. 68, pp. 4518-4522 (1990) shows that thermal annealing can be used to reduce dislocations in GaAs grown directly on (100) Si substrates. Their GaAs layers exhibit a dislocation density at or above 108 cm−2 prior to annealing. Using several annealing cycles they achieved dislocation densities as low as 3·106 cm−2. Yamaguchi et al. also shows a dependency between grown thicknesses and number of dislocations, and that the found dislocation density differs when using different examination techniques (EPD (Etch Pit Density) and TEM (Transmission Electron Microscopy)). The lowest number of dislocations was reported for the specimens at 3500 nm of GaAs on Si after 4 thermal annealing cycles to 900° C.
M. Umeno, T. Kato, M. Yang, Y Azuma, T. Soga, T. Jimbo: <<High efficiency AlGaAs/Si Tandem Solar Cell Over 20%>>, pp. 1679-1684, WCPEC, Hawaii (1994) demonstrated an AlGaAs/Si dual-junction solar cell with only a 10 nm thin GaAs buffer layer at the III-V/Si material interface. No other dislocation barrier was reported used to realise the top solar cell, but still obtained a working AlGaAs cell at a dislocation density of 2·107cm−2. From theoretical calculations they showed that a Al0.22Ga0.78As/Si dual-junction solar cell could obtain a total conversion efficiency of 32-33%. Their experimental cell was grown with an AlGaAs thickness of 3000 nm, and obtained a top Al0.15Ga0.85As and bottom Si cell efficiency of up to 11.9% and 8.92% respectively. In series the total dual-cell efficiency was shown to be up to 19.9%.
R. J. Malik, J. P. van der Ziel, B. F. Levine, C. G. Bethea and J. Walker: <<Molecular-Beam epitaxy of GaSb/AlSb optical device layers on Si(100)>>, Journal of Applied Physics, Vol. 59, No. 11 (1986) discloses that an AlSb containing layer on Si could enable growth of monocrystalline III-V material with lower dislocation density than what was previously achieved at the time. A pulsed deposition technique was used in which one monolayer of AlSb was deposited one at the time at 400° C. with a 15 s waiting time between the depositions of layers. After a 150 Å layer of AlSb was achieved with this method on Si, a 600 nm thick AlSb buffer at 550° C. was grown. R. J. Malik et al. then used a 50 period 10 nm AlSb/10 nm GaSb superlattice prior to growth of a GaSb/AlGaSb laser structure on top. They attribute the long wavelength of the optically-pumped laser to be due to a tensile stress in the GaSb film, but do not disclose any dislocation density values on their materials.
G. Balakrishnan, S. Huang, A. Khoshakhlagh, P. Hill, A. Amtout, S. Krishna, G. P. Donati, L. R. Dawson, D. L. Huffaker: “Room-temperature optically-pumped InGaSb quantum well lasers monolithically grown on Si(100) substrate”, Electronics Letters, v 41, n 9, p 531-2, 28 Apr. 2005 uses the same technique as Malik et al., but uses a substrate temperature of 500® C. during both the initial AlSb growth and subsequent AlSb buffer and AlSb/GaSb superlattice growth. After the superlattice, they grow a AlGaSb/InGaSb laser which is optically-pumped and emits at room-temperature. No dislocation density is mentioned, but in G. Balakrishnan, S. Huang, L. R. Dawson, Y.-C. Xin, P. Conlin, and D. L. Huffaker: “Growth mechanisms of highly mismatched AlSb on a Si substrate”, Applied Physics Letters, Vol. 86, pp. 034105-1-3 (2005) they describe the AlSb/Si nucleation process in more detail and mention a misfit dislocation density on the order of 1011 cm−2 in the initial AlSb layer.
Hideyuki Toyota, Tomonori Sasaki, Yoshio Jinbo, Naotaka Uchitomi: “Growth and characterization of GaSb/AlGaSb multi-quantum well structures on Si (001) substrates”, Journal of Crystal Growth, Vol. 310, pp. 78-82 (2008) use the same technique as Malik et al. for growth of AlSb/GaSb on Si. They compare the use of thick GaSb buffers with and without GaSb/AlGaSb superlattices with a GaSb/AlGaSb multi-quantum well on top. Although no dislocation density values are given, they show that the X-ray diffraction spectrum of the (004) peak has a full-width-half-maximum value of 0.245 degrees.
S. H. Huang, G. Balakrishnan, M. Mehta, A. Khoshakhlagh, L. R. Dawson, and D. L. Huffaker: “Epitaxial Growth and formation of interfacial misfit array for tensile GaAs on GaSb” Applied Physics Letters 90, 161902 (2007) disclose dislocation densities as low as 3·106cm−2 provided by a group V soak technique. They achieved this with GaAs on GaSb using an interfacial misfit layer that is formed using a method that relies on As overpressure. Their formation of defects is related to obtaining a Ga-rich surface, due to As exposure of GaSb. They do not report the dislocation density of their GaSb substrates, but commercially available substrates are available with a dislocation density measured by etch pit density (EPD) at 1000 cm−2 or 10000 cm−2.
According to an aspect of the present invention, harmful threading dislocation faults may be avoided if a dominant threading dislocation direction or stacking of faults does not take place in a direction parallel to or close to the direction of the epitaxial growth, or is stopped completely. For example, if threading dislocation faults are constrained to be parallel or at least close to parallel to a surface of a wafer, for example a Si wafer, the threading dislocations will not appear in the material that is grown in the process, The dislocation faults will be constrained at the surface or close to the surface of the wafer and therefore appear as location stabilised in respective positions at this interface. This controlling of the dislocation faults makes it possible to grow GaAs on top of a wafer providing low defect densities for the complete manufactured material. This aspect of the present invention is achieved by pre-processing steps comprising a controlled and defined temperature, pressure and time interval exposure of material combinations. The relation between these three parameters has been established experimentally.
According to an example of embodiment of the present invention, a method for epitaxial growth of III-V group materials on Si wafers comprises pre-processing steps executed before growing the actual III-V group materials on the Si wafer, wherein the pre-processing steps comprises growing a AlSb nucleation layer on top of the Si wafer followed by growing a GaSb layer on the AlSb nucleation layer, wherein this three layer composition is exposed to a low pressure condition over a certain time and substrate temperature. These pre-processing steps provides a defect density as low as 2000 cm−2 which is much lower compared to results reported in the prior art.